Parallel scrambler of exchange in asynchronous transfer mode

ABSTRACT

A parallel scrambler of an ATM exchange for mapping ATM cells to STM frames and transmitting data includes: a parallel pseudo-random binary sequence (PRBS) generator for selectively performing a logic operation with respect to two or more PRBSs which are shifted in parallel after being generated for scrambling of the ATM cells and outputting parallel PRBSs in synchronization with an input clock after latching a result of the operation; and a data scrambler for scrambling the parallel PRBSs generated by the parallel PRBS generator and data to be transmitted and latching and outputting scrambled dat.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a frame scrambler which is used when an exchange in an asynchronous transfer mode (ATM) maps ATM cells to synchronous transfer mode (STM) frames before transmission. Particularly, this invention relates to a parallel scrambler for lowering an operation speed when scrambling the ATM cells before mapping them to the frames over an STM-1 (155 Mbps) rate by scrambling the data in parallel in an ATM exchange, thereby saving electric power and improving reliability in data scrambling.

[0003] 2. Discussion of Related Art

[0004] In general, when mapping ATM cells to STM frames before transmitting data, the ATM cells are scrambled using a pseudo-random binary sequence (PRBS) formed based on a generator polynomial, X⁷+X⁶+1. FIG. 1 shows a conventional serial scrambler of an ATM exchange used when mapping the ATM cells to the STM frames and transmitting the data through such method.

[0005] As shown in FIG. 1, the conventional serial scrambler includes: a PRBS generator 10 having a number of shift registers SR1 to SR7 for shifting input signals at predetermined periods and an exclusive OR element for performing an exclusive OR operation with respect to each data from the sixth and seventh shift registers SR6 and SR7 and sending a result of the operation to the input port of the first shift register SR1; and an exclusive OR element 20 for performing the exclusive OR operation with respect to the PRBS which is generated through shifting by the PRBS generator 10 and data to be transmitted (data in) and outputting scrambled data as a result of the operation.

[0006] For such conventional serial scrambler, the PRBS generator 10 generates the PRBS using the generator polynomial, X⁷+X⁶+1, in such a manner of initially setting values of the first to seventh shift registers SR1 to SR7 to “1” using a set signal and outputting one bit of PRBS each time when a clock is generated.

[0007] When transmitting ATM cells based upon a synchronous digital hierarchy (SDH), the cells are scrambled just before being transmitted to the STM frames. So, as illustrated above, the exclusive OR operation with respect to the PRBS generated by the PRBS generator 10 and the data to be transmitted (data in) is performed by the exclusive OR element 20. The scrambled data which is the result of the operation is then transmitted to an STM framer.

[0008] When scrambling of the ATM cells before mapping them to STM-4 frames is performed by such serial scrambler, data must be inputted to the scrambler at 622.08 Mbps, so the PRBS generator 10 also must operate at the same speed. This is not good for embodiment of an electronic circuit and, moreover, integration of circuits. In other words, the circuit must be embodied using devices available for processing high speed signals, which is not economical and results in an increment of power consumption. This conventional serial scrambler which processes signals at the high speed has other drawbacks such as low reliability and low degree of circuit integration.

SUMMARY OF THE INVENTION

[0009] Accordingly, the present invention is directed to a parallel scrambler of an ATM exchange that substantially obviates one or more of the limitations and disadvantages of the related art.

[0010] An object of the present invention is to provide a parallel scrambler for lowering an operation speed when scrambling ATM cells for frames over an STM-1 (155 Mbps) rate by scrambling the data in parallel in an ATM exchange, thereby saving electric power and improving reliability in data scrambling.

[0011] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure as illustrated in the written description and claims hereof, as well as the appended drawings.

[0012] To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a parallel scrambler of an ATM exchange for mapping ATM cells to STM frames and transmitting data includes: a parallel pseudo-random binary sequence (PRBS) generator for selectively performing a logic operation with respect to two or more PRBSs which are shifted in parallel after being generated for scrambling of the ATM cells and outputting parallel PRBSs in synchronization with an input clock after latching a result of the operation; and a data scrambler for scrambling the parallel PRBSs generated by the parallel PRBS generator and data to be transmitted and latching and outputting scrambled data.

[0013] In case of transmitting the data at an STM-1 rate of 155 Mbps, the parallel PRBS generator includes: a PRBS logic unit for selecting two or more PRBSs among the parallel PRBSs which are previously generated for scrambling of the ATM cells and performing the exclusive OR operation with respect to the selected ones; a latch unit for latching the signals from the PRBS logic unit in synchronization with an input clock and generating parallel PRBSs; and an exclusive OR element for performing the exclusive OR operation with respect to first PRBS and second PRBS outputted from the latch unit to generate an eighth PRBS.

[0014] In case of transmitting data at an STM-1 rate of 155 Mbps, the data scrambler includes: an AND element for performing an AND operation with respect to a number of PRBSs generated by the parallel PRBS generator and an enable signal which is generated not to scramble frame alignment bytes; an exclusive OR element for performing an exclusive OR operation with respect to an output signal of the AND element and data to be transmitted; and a flip-flop for latching an output signal of the exclusive OR element according to the clock and outputting scrambled data.

[0015] In case of transmitting data at an STM-4 rate of 622 Mbps, the parallel PRBS generator includes: a PRBS logic unit for selecting two or more PRBSs among the parallel PRBSs which are previously generated for scrambling of the ATM cells and performing an exclusive OR operation with respect to the selected ones; a latch unit for latching a number of output signals of the PRBS logic unit in synchronization with an input clock and generating parallel PRBSs; and a logic unit for performing the exclusive OR operation with respect to two or more of output signals of the latch unit and outputting eighth to sixteenth PRBSs.

[0016] In case of transmitting data at an STM-4 rate of 622 Mbps, the data scrambler includes: an AND element for performing an AND operation with respect to a number of PRBSs from the parallel PRBS generator and an enable signal which is obtained not to scramble frame alignment bytes; an exclusive OR element for performing an exclusive OR operation with respect to an output signal of the AND element and data to be transmitted; and a flip-flop for latching an output signal of the exclusive OR element according to the clock and outputting scrambled data.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0019] In the drawings:

[0020]FIG. 1 is a block diagram of a conventional serial scrambler of an ATM exchange;

[0021]FIG. 2 is a block diagram of a parallel scrambler of an ATM exchange according to the present invention;

[0022]FIG. 3 shows a configuration of a parallel scrambler when data of 155 Mbps, an STM-1 rate, is transmitted in the present invention; and

[0023]FIG. 4 shows a configuration of a parallel scrambler when data of 622 Mbps, an STM-4 rate, is transmitted in the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

[0024] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0025] With reference to the attached drawings, a preferred embodiment of the present invention is described in detail below.

[0026] As shown in FIG. 2, the parallel scrambler of an ATM exchange according to the present invention includes: a parallel PRBS generator 1000 for selecting and performing a logic operation with respect to two or more PRBSs (r0-r6) which are shifted in parallel after being generated for scrambling of ATM cells and outputting parallel PRBSs in synchronization with an input clock after latching results of the operation; and a data scrambling unit 2000 for scrambling the parallel PRBSs generated by the parallel PRBS generator 1000 and data to be transmitted and latching and outputting scrambled data.

[0027] Specifically, the parallel PRBS generator 1000 selectively mixes the PRBSs (r0-r6) which are generated for mapping ATM cells to STM frames and generates the parallel PRBSs. The data scrambling unit 2000 then scrambles the ATM cell data using the parallel PRBSs generated by the parallel PRBS generator 1000.

[0028] This parallel scrambler of the present invention has different configuration according to classes of the STM rate. This is specifically described below.

[0029]FIG. 3 shows a configuration of a parallel scrambler when data of 155 Mbps, an STM-1 rate, is transmitted in the present invention. As show in FIG. 3, the parallel scrambler includes: a parallel PRBS generator 100 for selectively performing a logic operation with respect to two or more PRBSs (r0-r6) which are shifted in parallel and shifting a result of the operation in synchronization with an input clock so as to generate the parallel PRBSs (PRBS1-PRBS8); and a data scrambling unit 200 for scrambling the parallel PRBSs (PRBS1-PRBS8) generated by the parallel PRBS generator 100 and data to be transmitted (data_in[1:8]) and outputting scrambled data after latching a scrambled result.

[0030] The parallel PRBS generator 100 includes: a PRBS logic unit 110 for selecting two or more PRBSs among the seven PRBSs (r0-r6) which are previously generated for the ATM cell scrambling and performing the exclusive OR operation with respect to the selected ones; a latch unit 120 for latching the signals from the PRBS logic unit 110 in synchronization with an input clock and generating the parallel PRBSs (PRBS1-PRBS7); and an exclusive OR element 130 for performing the exclusive OR operation with respect to the first PRBS and second PRBS to generate an eighth PRBS.

[0031] The PRBS logic unit 110 has first to seventh exclusive OR elements 111 to 117 for selectively performing the exclusive OR operation with respect to two or more of the seven PRBSs (r0-r6).

[0032] The latch unit 120 has first through seventh flip-flops 121 to 127 for latching the signals from the first to seventh OR elements 111 to 117 in synchronization with the input clock and generating the first to seventh PRBSs.

[0033] The data scrambling unit 200 includes: an AND element 201 for performing an AND operation with respect to the first to eighth PRBSs (PRBS1-PRBS8) and an enable signal obtained not to scramble frame alignment bytes; an exclusive OR element 202 for performing the exclusive OR operation with respect to the output signal of the AND element 201 and the data to be transmitted (data_in[1:8]); and a flip-flop 203 for latching the output signal of the exclusive OR element 202 according to the clock and outputting the scrambled data (data_out[1:8]).

[0034] For the parallel scrambler having such configuration, eight PRBSs should be generated at one clock to scramble the data in parallel by 8 bits. The PRBS absolutely depends on the previous status of a register, so data generated from the first clock until the eighth clock and the register's status after the eighth clock is generated can be assumed. This is embodied in the parallel PRBS generator 100 depicted in FIG. 3. Each exclusive OR element 111 to 117 in the PRBS logic unit 110 performs the exclusive OR operation with respect to two or more PRBSs (r0-r6) which have been previously generated for the ATM cell scrambling and transmits the operated results to the latch unit 120. The latch unit 120 sequentially shifts the signals from each OR element by one bit in synchronization with the input clock so as to output first to seventh PRBSs (PRBS1-PRBS7). The exclusive OR element 130 performs the exclusive OR operation with respect to the first and second PRBSs respectively generated by the first and second flip-flops 121 and 122 to generate the eighth PRBS.

[0035] More specifically, when t=T (T is a period of time of a clock), the status of each register and an output PRBS after one clock is inputted appears as follows.

[0036] The value of the second flip-flop 122, r1, is inputted to the first flip-flop 121; r2, to the second flip-flop 122; r3, to the third flip-flop 123; r4, to the fourth flip-flop 124; r5, to the fifth flip-flop 125; r6, to the sixth flip-flop 126; and a result of the exclusive OR operation of the r1 and r0, to the seventh flip-flop 127. The output PRBS is a value generated by the first flip-flop 121.

[0037] The above co-relation can be expressed as the formula,

[0038] r0(T)=r1(0)

[0039] r1(T)=r2(0)

[0040] r2(T)=r3(0)

[0041] r3(T)=r4(0)

[0042] r4(T)=r5(0)

[0043] r5(T)=r6(0)

[0044] r6(T)=r0(0)⊕r1(0)

[0045] Output PRBS=r0(0).

[0046] Since the above co-relation is repeated every clock, for the convenience of calculation, the above formula can be expressed as a vector as follows. ${R(T)} = {{A \cdot {R(0)} \cdot A} = {\left| \begin{matrix} 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R(T)} \right. = \left| \begin{matrix} {{r0}(T)} \\ {{r1}(T)} \\ {{r2}(T)} \\ {{r3}(T)} \\ {{r4}(T)} \\ {{r5}(T)} \\ {{r6}(T)} \end{matrix} \right|}}}$

[0047] When calculating the output PRBS until t=8T (8 clocks) according to the above principle, the result is as follows. For example,

[0048] when t=2T, R(2T) = A² ⋅ R(0) $A^{2} = {\left| \begin{matrix} 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {2T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {2T} \right)} \\ {{r1}\left( {2T} \right)} \\ {{r2}\left( {2T} \right)} \\ {{r3}\left( {2T} \right)} \\ {{r4}\left( {2T} \right)} \\ {{r5}\left( {2T} \right)} \\ {{r6}\left( {2T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad S} \right. = {{{r0}(T)} = {{{r1}(0)}.}}}}}$

[0049] when t=3T, R(3T) = A³ ⋅ R(0) $A^{3} = {\left| \begin{matrix} 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {3T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {3T} \right)} \\ {{r1}\left( {3T} \right)} \\ {{r2}\left( {3T} \right)} \\ {{r3}\left( {3T} \right)} \\ {{r4}\left( {3T} \right)} \\ {{r5}\left( {3T} \right)} \\ {{r6}\left( {3T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t{\quad \quad}P\quad R\quad B\quad S} \right. = {{{r0}\left( {2T} \right)} = {{{r2}(0)}.}}}}}$

[0050] when t=4T, R(4T) = A⁴ ⋅ R(0) $A^{4} = {\left| \begin{matrix} 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {4T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {4T} \right)} \\ {{r1}\left( {4T} \right)} \\ {{r2}\left( {4T} \right)} \\ {{r3}\left( {4T} \right)} \\ {{r4}\left( {4T} \right)} \\ {{r5}\left( {4T} \right)} \\ {{r6}\left( {4T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad S} \right. = {{{r0}\left( {3T} \right)} = {{{r3}(0)}.}}}}}$

[0051] when t=5T, R(5T) = A⁵ ⋅ R(0) $A^{5} = {\left| \begin{matrix} 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {5T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {5T} \right)} \\ {{r1}\left( {5T} \right)} \\ {{r2}\left( {5T} \right)} \\ {{r3}\left( {5T} \right)} \\ {{r4}\left( {5T} \right)} \\ {{r5}\left( {5T} \right)} \\ {{r6}\left( {5T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad S} \right. = {{{r0}\left( {4T} \right)} = {{{r4}(0)}.}}}}}$

[0052] when t=6T, R(6T) = A⁶ ⋅ R(0) $A^{6} = {\left| \begin{matrix} 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {6T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {6T} \right)} \\ {{r1}\left( {6T} \right)} \\ {{r2}\left( {6T} \right)} \\ {{r3}\left( {6T} \right)} \\ {{r4}\left( {6T} \right)} \\ {{r5}\left( {6T} \right)} \\ {{r6}\left( {6T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad S} \right. = {{{r0}\left( {5T} \right)} = {{{r5}(0)}.}}}}}$

[0053] when t=7T, R(7T) = A⁷ ⋅ R(0) $A^{6} = {\left| \begin{matrix} 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {7T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {7T} \right)} \\ {{r1}\left( {7T} \right)} \\ {{r2}\left( {7T} \right)} \\ {{r3}\left( {7T} \right)} \\ {{r4}\left( {7T} \right)} \\ {{r5}\left( {7T} \right)} \\ {{r6}\left( {7T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad S} \right. = {{{r0}\left( {6T} \right)} = {{{r6}(0)}.}}}}}$

[0054] when t=8T, R(8T) = A⁸ ⋅ R(0) $A^{6} = {\left| \begin{matrix} 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {8T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {8T} \right)} \\ {{r1}\left( {8T} \right)} \\ {{r2}\left( {8T} \right)} \\ {{r3}\left( {8T} \right)} \\ {{r4}\left( {8T} \right)} \\ {{r5}\left( {8T} \right)} \\ {{r6}\left( {8T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad {S:{{r0}\left( {7T} \right)}}} \right. = {{{r0}(0)} \oplus {{{r1}(0)}.}}}}}$

[0055] To satisfy the above conditions, all the flip-flops 121 to 127 are initially set to “1” using a set terminal and made to generate eight PRBSs after one clock. Since the operating clock transmitted to each flip-flop 121 to 127 is processed in parallel by 8 bits, in case of an STM-1 (155.52 Mbps) rate, a clock of 19.44 MHz is inputted. The AND element 201 in the data scrambling unit 200 performs the AND operation with respect to the 8 bits parallel PRBS (PRBS1-PRBS8) and the enable signal and applies an operated result to an input port of the exclusive OR element 202. Performing the AND operation of the 8 bins parallel PRBS and enable signal is for preventing scrambling of the frame alignment bytes in the STM frames.

[0056] The exclusive OR element 202 performs the exclusive OR operation with respect to the output signal of the AND element 201 and the 8-bit data to be transmitted (data_in[1:8]) in order to scramble the data. The flip-flop 203 latches the scrambled data in synchronization with the clock and sends the transmission data to the STM framer, so the data is formatted as the STM frame.

[0057]FIG. 4 shows a configuration of a parallel scrambler when data of 622 Mbps, an STM-4 rate, is transmitted in the present invention.

[0058] This is a 16-bit parallel scrambler which includes: a parallel PRBS generator 300 for selecting and performing a logic operation with respect to two or more PRBSs (r0-r6) which are shifted in parallel and shifting a result of the operation in synchronization with an input clock so as to generate parallel PRBSs (PRBS1-PRBS16); and a data scrambling unit 400 for scrambling the parallel PRBSs (PRBS1-PRBS16) generated by the parallel PRBS generator 300 and data to be transmitted and outputting scrambled data after latching a scrambled result.

[0059] The parallel PRBS generator 300 includes: a PRBS logic unit 310 for selecting two or more PRBSs among the seven PRBSs (r0-r6) and performing an exclusive OR operation with respect to the selected ones; a latch unit 330 for latching the signals from the PRBS logic unit 310 in synchronization with the input clock and generating the parallel PRBS (PRBS1-PRBS7); and a logic unit 340 for performing the exclusive OR operation with respect to two or more output signals (r0-r6) of the latch unit 330 to generate the eighth through sixteenth PRBSs.

[0060] The PRBS logic unit 310 has first to eleventh exclusive OR elements 311 to 321 for selectively performing the exclusive OR operation with respect to two or more of the seven PRBSs (r0-r6) The latch unit 330 has first through seventh flip-flops 331 to 337 for latching the signals from the first to eleventh OR elements 311 to 321 in synchronization with the input clock and generating the first to seventh PRBSs.

[0061] The logic unit 340 has a number of exclusive OR elements 341 to 349 for selectively performing the exclusive OR operation with respect to the two or more output signals (r0-r6) of the flip-flops 331 to 337 and outputting operated results as the eighth to sixteenth PRBSs.

[0062] The data scrambling unit 400 includes: an AND element 401 for performing an AND operation with respect to the first to sixteenth PRBSs (PRBS1-PRBS16) and an enable signal which is obtained not to scramble frame alignment bytes; an exclusive OR element 402 for performing the exclusive OR operation with respect to the output signal of the AND element 401 and the data to be transmitted (data_in[1:16]); and a flip-flop 403 for latching the output signal of the exclusive OR element 402 according to the clock and outputting scrambled data (data_out[1:16]).

[0063] For this parallel scrambler having such configuration, 16 PRBSs should be generated at one clock to scramble the data in parallel by 16 bits. The PRBS absolutely depends on the previous status of a register, so data generated from the first clock until the 16th clock and the register's status after the 16th clock is generated can be assumed.

[0064] This is embodied in the parallel PRBS generator 300 depicted in FIG. 4. Each exclusive OR element 311 to 321 in the PRBS logic unit 310 performs the exclusive OR operation with respect to the two or more PRBSs (r0-r6) which have been previously generated and transmits the operated results to the latch unit 330. The latch unit 330 sequentially shifts the signals from each OR element by one bit in synchronization with the input clock and generate the first to seventh PRBSs (PRBS1-PRBS7). The logic unit 340 performs the exclusive OR operation with respect to the first to seventh PRBSs (r0-r6) respectively generated by the first to seventh flip-flops 331 to 337 to generate the eighth to sixteenth PRBSs (PRBS8-PRBS16).

[0065] More specifically, when t=T (T is a period of time of a clock), the status of each register and an output PRBS after one clock is inputted appears as follows.

[0066] The value of the second flip-flop 332, r1, is inputted to the first flip-flop 331; r2, to the second flip-flop 332; r3, to the third flip-flop 333; r4, to the fourth flip-flop 334; r5, to the fifth flip-flop 335; r6, to the sixth flip-flop 336; and a result of the exclusive OR operation of the r1 and r0, to the seventh flip-flop 337. The output PRBS is a value generated by the first flip-flop 331.

[0067] The above co-relation can be expressed as the formula,

[0068] r0(T)=r1(0)

[0069] r1(T)=r2(0)

[0070] r2(T)=r3(0)

[0071] r3(T)=r4(0)

[0072] r4(T)=r5(0)

[0073] r5(T)=r6(0)

[0074] r6(T)=r0(0)⊕r1(0)

[0075] Output PRBS=r0(0)

[0076] Since the above co-relation is repeated every clock, for the convenience of calculation, the above formula can be expressed as a vector as follows. R(T) = A ⋅ R(0) $A = {\left| \begin{matrix} 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R(T)} \right. = \left| \begin{matrix} {{r0}(T)} \\ {{r1}(T)} \\ {{r2}(T)} \\ {{r3}(T)} \\ {{r4}(T)} \\ {{r5}(T)} \\ {{r6}(T)} \end{matrix} \right|}}$

[0077] When calculating the output PRBS until t=16T (16 clocks) according to the above principle, the result is as follows. For example,

[0078] when t=2T, R(2T) = A² ⋅ R(0) $A^{2} = {\left| \begin{matrix} 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \end{matrix} \middle| \quad {R(0)} \right. = \quad {\left| \begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix} \middle| \quad {R\left( {2T} \right)} \right. = {\left| \begin{matrix} {{r0}\left( {2T} \right)} \\ {{r1}\left( {2T} \right)} \\ {{r2}\left( {2T} \right)} \\ {{r3}\left( {2T} \right)} \\ {{r4}\left( {2T} \right)} \\ {{r5}\left( {2T} \right)} \\ {{r6}\left( {2T} \right)} \end{matrix} \middle| {O\quad u\quad t\quad p\quad u\quad t\quad P\quad R\quad B\quad S} \right. = {{{r0}(T)} = {{r1}(0)}}}}}$

[0079] when t=3T, R(3T) = A^(j) ⋅ R(0) $A^{3} = {\begin{matrix} 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {3T} \right)}} = {\begin{matrix} {{r0}\quad \left( {3T} \right)} \\ {{r1}\left( {3T} \right)} \\ {{r2}\left( {3T} \right)} \\ {{r3}\left( {3T} \right)} \\ {{r4}\left( {3T} \right)} \\ {{r5}\left( {3T} \right)} \\ {{r6}\left( {3T} \right)} \end{matrix}}}$ Output  PRBS = r0(2T) = r2(0)

[0080] when t=4T, R(4T) = A⁴ ⋅ R(0) $A^{4} = {\begin{matrix} 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {4T} \right)}} = {\begin{matrix} {{r0}\quad \left( {4T} \right)} \\ {{r1}\left( {4T} \right)} \\ {{r2}\left( {4T} \right)} \\ {{r3}\left( {4T} \right)} \\ {{r4}\left( {4T} \right)} \\ {{r5}\left( {4T} \right)} \\ {{r6}\left( {4T} \right)} \end{matrix}}}$ Output  PRBS = r0(3T) = r3(0)

[0081] when t=5T, R(5T) = A⁵ ⋅ R(0) $A^{5} = {\begin{matrix} 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {5T} \right)}} = {\begin{matrix} {{r0}\quad \left( {5T} \right)} \\ {{r1}\left( {5T} \right)} \\ {{r2}\left( {5T} \right)} \\ {{r3}\left( {5T} \right)} \\ {{r4}\left( {5T} \right)} \\ {{r5}\left( {5T} \right)} \\ {{r6}\left( {5T} \right)} \end{matrix}}}$ Output  PRBS = r0(4T) = r4(0)

[0082] when t=6T, R(6T) = A⁶ ⋅ R(0) $A^{6} = {\begin{matrix} 0 & 0 & 0 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {6T} \right)}} = {\begin{matrix} {{r0}\quad \left( {6T} \right)} \\ {{r1}\left( {6T} \right)} \\ {{r2}\left( {6T} \right)} \\ {{r3}\left( {6T} \right)} \\ {{r4}\left( {6T} \right)} \\ {{r5}\left( {6T} \right)} \\ {{r6}\left( {6T} \right)} \end{matrix}}}$ Output  PRBS = r0(5T) = r5(0)

[0083] when t=7T, R(7T) = A⁷ ⋅ R(0) $A^{7} = {\begin{matrix} 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {7T} \right)}} = {\begin{matrix} {{r0}\quad \left( {7T} \right)} \\ {{r1}\left( {7T} \right)} \\ {{r2}\left( {7T} \right)} \\ {{r3}\left( {7T} \right)} \\ {{r4}\left( {7T} \right)} \\ {{r5}\left( {7T} \right)} \\ {{r6}\left( {7T} \right)} \end{matrix}}}$ Output  PRBS = r0(6T) = r6(0)

[0084] when t=8T, R(8T) = A⁸ ⋅ R(0) $A^{8} = {\begin{matrix} 0 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {8T} \right)}} = {\begin{matrix} {{r0}\quad \left( {8T} \right)} \\ {{r1}\left( {8T} \right)} \\ {{r2}\left( {8T} \right)} \\ {{r3}\left( {8T} \right)} \\ {{r4}\left( {8T} \right)} \\ {{r5}\left( {8T} \right)} \\ {{r6}\left( {8T} \right)} \end{matrix}}}$ Output  PRBS : r0(7T) = r0(0) ⊕ r1(0)

[0085] when t=9T, R(9T) = A⁹ ⋅ R(0) $A^{9} = {\begin{matrix} 0 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {8T} \right)}} = {\begin{matrix} {{r0}\quad \left( {9T} \right)} \\ {{r1}\left( {9T} \right)} \\ {{r2}\left( {9T} \right)} \\ {{r3}\left( {9T} \right)} \\ {{r4}\left( {9T} \right)} \\ {{r5}\left( {9T} \right)} \\ {{r6}\left( {9T} \right)} \end{matrix}}}$ Output  PRBS : r0(8T) = r1(0) ⊕ r2(0)

[0086] when t=10T, R(10T) = A¹⁰ ⋅ R(0) $A^{10} = {\begin{matrix} 0 & 0 & 0 & 1 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {10T} \right)}} = {\begin{matrix} {{r0}\quad \left( {11T} \right)} \\ {{r1}\left( {11T} \right)} \\ {{r2}\left( {11T} \right)} \\ {{r3}\left( {11T} \right)} \\ {{r4}\left( {11T} \right)} \\ {{r5}\left( {11T} \right)} \\ {{r6}\left( {11T} \right)} \end{matrix}}}$ Output  PRBS : r0(9T) = r2(0) ⊕ r3(0)

[0087] when t=11T, R(11T) = A¹¹ ⋅ R(0) $A^{11} = {\begin{matrix} 0 & 0 & 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {11T} \right)}} = {\begin{matrix} {{r0}\quad \left( {10T} \right)} \\ {{r1}\left( {10T} \right)} \\ {{r2}\left( {10T} \right)} \\ {{r3}\left( {10T} \right)} \\ {{r4}\left( {10T} \right)} \\ {{r5}\left( {10T} \right)} \\ {{r6}\left( {10T} \right)} \end{matrix}}}$ Output  PRBS : r0(10T) = r3(0) ⊕ r4(0)

[0088] when t=12T, R(12T) = A¹² ⋅ R(0) $A^{12} = {\begin{matrix} 0 & 0 & 0 & 0 & 0 & 1 & 1 \\ 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 \end{matrix}}$ ${R(0)} = {{{\begin{matrix} {{r0}(0)} \\ {{r1}(0)} \\ {{r2}(0)} \\ {{r3}(0)} \\ {{r4}(0)} \\ {{r5}(0)} \\ {{r6}(0)} \end{matrix}}\quad {R\left( {12T} \right)}} = {\begin{matrix} {{r0}\quad \left( {12T} \right)} \\ {{r1}\left( {12T} \right)} \\ {{r2}\left( {12T} \right)} \\ {{r3}\left( {12T} \right)} \\ {{r4}\left( {12T} \right)} \\ {{r5}\left( {12T} \right)} \\ {{r6}\left( {12T} \right)} \end{matrix}}}$ Output  PRBS : r0(11T) = r4(0) ⊕ r5(0)

[0089] when t=13T, R(13T) = A¹³ ⋅ R(0) $A^{13} = {{{\begin{matrix} 1 & 1 & 0 & 0 & 0 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 \end{matrix}}{R(0)}} = {{{\begin{matrix} {{r0}\quad (0)} \\ {{r1}\quad (0)} \\ {{r2}\quad (0)} \\ {{r3}\quad (0)} \\ {{r4}\quad (0)} \\ {{r5}\quad (0)} \\ {{r6}\quad (0)} \end{matrix}}{R\left( {13T} \right)}} = {\begin{matrix} {{r0}\quad \left( {13T} \right)} \\ {{r1}\quad \left( {13T} \right)} \\ {{r2}\quad \left( {13T} \right)} \\ {{r3}\quad \left( {13T} \right)} \\ {{r4}\quad \left( {13T} \right)} \\ {{r5}\quad \left( {13T} \right)} \\ {{r6}\quad \left( {13T} \right)} \end{matrix}}}}$ Output  PRBS : r0  (12T) = r5(0) ⊕ r6(0)

[0090] when t=14T, R(14T) = A¹⁴ ⋅ R(0) $A^{14} = {{{\begin{matrix} 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 1 \end{matrix}}{R(0)}} = {{{\begin{matrix} {{r0}\quad (0)} \\ {{r1}\quad (0)} \\ {{r2}\quad (0)} \\ {{r3}\quad (0)} \\ {{r4}\quad (0)} \\ {{r5}\quad (0)} \\ {{r6}\quad (0)} \end{matrix}}{R\left( {14T} \right)}} = {\begin{matrix} {{r0}\quad \left( {14T} \right)} \\ {{r1}\quad \left( {14T} \right)} \\ {{r2}\quad \left( {14T} \right)} \\ {{r3}\quad \left( {14T} \right)} \\ {{r4}\quad \left( {14T} \right)} \\ {{r5}\quad \left( {14T} \right)} \\ {r\quad 6\quad \left( {14T} \right)} \end{matrix}}}}$ Output  PRBS : r0  (13T) = r0(0) ⊕ r1(0) ⊕ r6(0)

[0091] when t=15T, R(15T) = A¹⁵ ⋅ R(0) $A^{15} = {{{\begin{matrix} 0 & 1 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 1 \\ 1 & 1 & 1 & 1 & 0 & 0 & 0 \end{matrix}}{R(0)}} = {{{\begin{matrix} {{r0}\quad (0)} \\ {{r1}\quad (0)} \\ {{r2}\quad (0)} \\ {{r3}\quad (0)} \\ {{r4}\quad (0)} \\ {{r5}\quad (0)} \\ {{r6}\quad (0)} \end{matrix}}{R\left( {15T} \right)}} = {\begin{matrix} {{r0}\quad \left( {15T} \right)} \\ {{r1}\quad \left( {15T} \right)} \\ {{r2}\quad \left( {15T} \right)} \\ {{r3}\quad \left( {15T} \right)} \\ {{r4}\quad \left( {15T} \right)} \\ {{r5}\quad \left( {15T} \right)} \\ {r\quad 6\quad \left( {15T} \right)} \end{matrix}}}}$ output  PRBS : r0  (14T) = r1(0) ⊕ r2(0)

[0092] when t=16T, R(16T) = A¹⁶ ⋅ R(0) $A^{16} = {{{\begin{matrix} 0 & 0 & 1 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 1 \\ 1 & 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 1 & 1 & 1 & 1 & 0 & 0 \end{matrix}}R(0)} = {{{\begin{matrix} {{r0}\quad (0)} \\ {{r1}\quad (0)} \\ {{r2}\quad (0)} \\ {{r3}\quad (0)} \\ {{r4}\quad (0)} \\ {{r5}\quad (0)} \\ {{r6}\quad (0)} \end{matrix}}{R\left( {16T} \right)}} = {\begin{matrix} {{r0}\quad \left( {16T} \right)} \\ {{r1}\quad \left( {16T} \right)} \\ {{r2}\quad \left( {16T} \right)} \\ {{r3}\quad \left( {16T} \right)} \\ {{r4}\quad \left( {16T} \right)} \\ {{r5}\quad \left( {16T} \right)} \\ {r\quad 6\quad \left( {16T} \right)} \end{matrix}}}}$ output  PRBS : r0  (15T) = r1(0) ⊕ r3(0).

[0093] To satisfy the above conditions, all the flip-flops 321 to 327 are initially set to “1” using a set terminal and made to generate the 16 PRBSs after one clock. Since the operating clock transmitted to each flip-flop 321 to 327 is processed in parallel by 16 bits, in case of an STM-4 (622.08 Mbps) rate, a clock of 38.88 MHz is inputted. The AND element 401 in the data scrambling unit 400 performs the AND operation with respect to the 16 bits parallel PRBS (PRBS1-PRBS16) and the enable signal and applies an operated result to an input port of the exclusive OR element 402. Performing the AND operation of the 16 bits parallel PRBS and enable signal is for preventing scrambling of the frame alignment bytes in the STM frames.

[0094] The exclusive OR element 402 performs the exclusive OR operation with respect to the output signal of the AND element 401 and the 16-bit data to be transmitted (data_in[1:16]) to scramble the data. The flip-flop 403 latches the scrambled data in synchronization with the clock and sends the transmission data to the STM framer, so the data is formatted as the STM frame.

[0095] As illustrated above, the present invention processes data in parallel by 8 bits or 16 bits when scrambling the data of an STM-1 rate of 155 Mbps or an STM-4 rate of 622 Mbps, allowing a low speed process (155M/8=19.44M, 622M/16=38.88M), thereby constructing a scrambler with cheaper devices without using expensive devices. In addition, the present invention does not use high speed devices, thereby saving electric power and improving reliability and integration.

[0096] It will be apparent to those skilled in the art that various modifications and variations can be made in a parallel scrambler of an ATM exchange of the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. 

What is claimed is:
 1. A parallel scrambler of an ATM exchange for mapping ATM cells to STM frames and transmitting data comprising: parallel pseudo-random binary sequence (PRBS) generation means for selectively performing a logic operation with respect to two or more PRBSs which are shifted in parallel after being generated for scrambling of the ATM cells and outputting parallel PRBSs in synchronization with an input clock after latching a result of the operation; and data scrambling means for scrambling the parallel PRBSs generated by the parallel PRBS generation means and data to be transmitted and latching and outputting scrambled data.
 2. The scrambler according to claim 1, wherein, in case of transmitting the data at an STM-1 rate of 155 Mbps, the parallel PRBS generation means comprises: a PRBS logic unit for selecting two or more PRBSs among the parallel PRBSs which are previously generated for scrambling of the ATM cells and performing the exclusive OR operation with respect to the selected ones; a latch unit for latching the signals from the PRBS logic unit in synchronization with an input clock and generating parallel PRBSs; and an exclusive OR element for performing the exclusive OR operation with respect to first PRBS and second PRBS outputted from the latch unit to generate an eighth PRBS.
 3. The scrambler according to claim 2, wherein the PRBS logic unit has first to seventh exclusive OR elements for selectively performing the exclusive OR operation with respect to two or more of the parallel PRBSs.
 4. The scrambler according to claim 2, wherein the latch unit has first through seventh flip-flops for latching the signals from first to seventh OR elements in the PRBS logic unit in synchronization with an input clock and generating first to seventh PRBSs.
 5. The scrambler according to claim 3, wherein the latch unit has first through seventh flip-flops for latching the signals from the first to seventh OR elements in the PRBS logic unit in synchronization with an input clock and generating first to seventh PRBSs.
 6. The scrambler according to claim 1, wherein, in case of transmitting data at an STM-1 rate of 155 Mbps, the data scrambling means comprises: an AND element for performing an AND operation with respect to a number of PRBSs generated by the parallel PRBS generation means and an enable signal which is generated not to scramble frame alignment bytes; an exclusive OR element for performing an exclusive OR operation with respect to an output signal of the AND element and data to be transmitted; and a flip-flop for latching an output signal of the exclusive OR element according to the clock and outputting scrambled data.
 7. The scrambler according to claim 1, wherein, in case of transmitting data at an STM-4 rate of 622 Mbps, the parallel PRBS generation means comprises: a PRBS logic unit for selecting two or more PRBSs among the parallel PRBSs which are previously generated for scrambling of the ATM cells and performing an exclusive OR operation with respect to the selected ones; a latch unit for latching a number of output signals of the PRBS logic unit in synchronization with an input clock and generating parallel PRBSs; and a logic unit for performing the exclusive OR operation with respect to two or more of output signals of the latch unit and outputting eighth to sixteenth PRBSs.
 8. The scrambler according to claim 7, wherein the PRBS logic unit has first to eleventh exclusive OR elements for selectively performing the exclusive OR operation with respect to two or more of the parallel PRBSs which are generated for scrambling of the ATM cells.
 9. The scrambler according to claim 7, wherein the latch unit has first through seventh flip-flops for latching the output signals of the PRBS logic unit in synchronization with the input clock and generating the parallel first to seventh PRBSs.
 10. The scrambler according to claim 7, wherein the logic unit has a number of exclusive OR elements for selectively performing the exclusive OR operation with respect to the two or more output signals of first to seventh flip-flops in the latch unit and outputting the eighth to sixteenth PRBSs.
 11. The scrambler according to claim 1, wherein, in case of transmitting data at an STM-4 rate of 622 Mbps, the data scrambling means comprises: an AND element for performing an AND operation with respect to a number of PRBSs from the parallel PRBS generation means and an enable signal which is obtained not to scramble frame alignment bytes; an exclusive OR element for performing an exclusive OR operation with respect to an output signal of the AND element and data to be transmitted; and a flip-flop for latching an output signal of the exclusive OR element according to the clock and outputting scrambled data. 